Microchip fabrication involves the formation of integrated circuits (ICs) on a semiconducting substrate. A large number of semiconductor devices or ICs are typically constructed on a single substrate or wafer of a single crystal silicon material. The area on the wafer occupied by the discrete devices or ICs is called a chip or die. After formation, the individual chips are separated and connected by gold wires to a lead frame. Typically the chips are then packaged in a plastic or ceramic package that is necessary to protect the chip and provide a substantial electrical lead system. For forming electronic devices a number of chips are electrically connected on printed circuit boards by techniques such as socketing or soldering.
Within an individual chip a large number of discrete individual electrical devices are formed. These separate devices are interconnected using conductive metal lines or traces formed by patterning metal layers deposited onto the substrate. Signals, such as pulsating DC signals and AC signals, are routed over the metal traces to the devices. Most commonly, the signals are routed in aluminum metal, which provides the lowest resistivity of the thin films available in integrated circuit manufacture. Often several conductive traces are routed adjacent to each other in an area expressly allocated for signal routing (bussing). These traces can run parallel to one another for several millimeters.
Signal traces are driven by transistors which switch the voltage levels very rapidly. The close proximity of other structure (such as signal traces) and other layers (such as substrate) results in capacitive coupling to the signal traces. Switching of the voltage level of a signal trace can result in a corresponding inadvertent change in a voltage level on a nearby signal trace or layer, resulting in logic errors.
As an example, an alternating current signal, such as a clock signal, or a pulsating direct current, will be capacitively coupled into the substrate. This capacitive coupling will result in unwanted noise in the substrate. This noise will likely be carried by the substrate into nearby circuitry and may cause circuit malfunctions such as mistriggering.
U.S. patent application Ser. No. 683,767 to Hesson et al., entitled Low-Noise, Area-Efficient, High-Frequency Clock Signal Distribution Line Structure, and assigned to the assignee of the present application, discloses a transmission line structure for decoupling high-frequency signals carried by a signal line from a subjacent substrate. This application is largely concerned with clock lines which cover a large physical area on an IC and therefore couple proportionately to the substrate.
Another type of capacitive coupling can occur between adjacent conductive traces. This type of capacitive coupling though on a smaller area scale is comparable to the coupling between a conductive trace and the substrate or ground plane and can produce similar logic errors. FIG. 1A illustrates such a situation.
With reference to FIG. 1A a semiconductor structure includes conductive traces 10, 12 in the form of two parallel metal lines formed on an oxide layer 14 above a grounded substrate 16. Conductive trace 10 carries a signal 1 and conductive trace 12 carries a signal 2 to semiconductor devices (not shown). The conductive traces 10, 12 are spaced (center to center) a distance equal to the metal pitch (Pm) attainable by the particular fabrication technology. In state of the art technologies, such as VLSI and ULSI, the metal pitch (Pm) is comparable to the vertical separation from the conductive traces 10 12 to the substrate 16. Likewise, the capacitance (Cc) between the conductive traces 10, 12 is comparable to the capacitance (Cg) from the conductive traces 10, 12 to the substrate 16.
The electrical schematic shown in FIG. 1B represents an electrical model of the two unshielded parallel conductive traces 10, 12 (i.e. the structure shown in FIG. 1A). FIG. 1C illustrates the affect when conductive trace 10 or 12 experiences a rapid change in potential (i.e. in switching from one logic level to another). Since a finite impedance (Rd) exists between the point of coupling of Signal 1 and the driver of Signal 2, the response of Signal 2 will be to shift with Signal 1 until the driver can restore the original voltage level. The magnitude of the noise "bump" at Signal 2 is proportional to the ratio of Cc and Cg. A larger Cc/Cg ratio results in more cross coupling between the conductive traces 10 or 12. If Signal 2 is a direct action signal such as a reset or clock line, a spurious transition due to cross coupling between the conductive traces 10 or 12 can result in circuit failure.
Note that there are at least four cases of interest regarding the voltage levels present on conductive trace 10 and conductive trace 12: 1) one signal low and the other transitioning between a low level and a high level; 2) one signal high and the other transitioning from a high level to a low level; 3) one signal high and the other transitioning from a low level to a high level: 4) one signal low and the other transitioning from a high level to a low level.
Generally, only cases 1 and 2 above will cause logic errors due to spurious transitions, but cases 3 and 4 are of concern also in that the "static" signal can be boosted above the power supply voltage (case 3) or below ground (case 4), resulting in charge injection through diffusions into the substrate or well. Such injections can cause loss of data at dynamic storage nodes (i.e. DRAM cells) or, at worst, latchup.
With reference to FIG. 2A, one prior art method used to reduce cross-coupling between adjacent conductive traces on a semiconductor substrate is to move the ground plane nearer the conductive traces 10, 12. This could be accomplished, for example, by placing a conductive material such as a layer of polysilicon 18 beneath the conductive traces 10, 12 and tying the polysilicon 18 to the grounded substrate 16. In this case the capacitance coupling to ground Cg is increased, since the physical separation from the conductive traces 10, 12 to ground has decreased. Similarly, a cross coupling (Cc) between the conductive traces 10, 12 is reduced and the ratio of Cg/Cc increases. This helps only marginally, however, since the reduction in separation between the conductive traces and substrate is dependant upon the relative thicknesses of the dielectric or oxide 14 between the conductive traces 10, 12 and substrate 16 and the dielectric 20 between the polysilicon 18 and the conductive traces 10, 12. As is apparent, on a vertical level, these distances will not be large. In addition the polysilicon 18 shielding layer is not physically located between the conductive traces 10, 12, but rather is orthogonal to the coupling direction from the conductive traces 10, 12 to the substrate 16. Accordingly the direct effect on cross coupling between the conductive traces 10, 12 is minimal.
With reference to FIGS. 2B and 2C, a second prior art approach taken to reduce cross coupling between conductive traces 10, 12 is to introduce another metal line or a shielding trace 22 between the conductive traces 10, 12. The capacitance to ground (Cg) for either trace 10, 12 is now the sum of the capacitance to substrate (Cg1) and the capacitance (Cg2) to the shielding trace 22. The magnitude of the noise on metal line 12 as a result of a transition on metal line 10 is proportional to the ratio of Cc to Cg (the sum of Cg1 and Cg2). The net effect of adding a grounded metal line as a shielding trace 22 is: 1) increased separation between conductive traces 10,12 leading to a lower Cc, but at a cost of more area; 2) increased signal capacitance to ground, thereby reducing the ratio of cross coupling to ground capacitance (i.e. Cc/Cg). While this technique works very well in reducing cross coupling between the conductive traces 10,12, the penalty is severe in that the layout area required to pattern the conductive traces 10,12 is doubled (i.e. line to line spacing is now 2XPm).
The present invention is directed to a novel shielding structure for adjacent conducting traces that overcomes these prior art limitations. Accordingly, it is an object of the present invention to provide a shielding structure that is effective for reducing cross coupling between adjacent conducting traces and increasing capacitive coupling between conducting traces and ground in a semiconductor structure. It is another object of the present invention to provide a shielding structure that is effective for reducing cross coupling between the conducting traces but without using a layout area of the conducting traces.